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Arasan MIPI CSI-2 v2.1 Receiver IP

The CSI-2 v2.1 Receiver product page reviewed on 12 November 2026 describes a MIPI CSI-2 Combo Receiver that interfaces a camera module to a host processor or image-processing block over a D-PHY or C-PHY link.

Overview

The CSI-2 transmitter and the analog PHY are separate products on Arasan’s MIPI pages.

The page names compliance with CSI-2 specification v2.1, D-PHY specification v2.1, D-PHY specification v1.2, and C-PHY specification v1.2. It states lane configurations up to 8-lane D-PHY or 3-lane C-PHY, Ultra Low Power Mode, virtual-channel extension (16 virtual channels in D-PHY mode and 32 in C-PHY mode), and pixel-format families including RAW, YUV, and RGB types listed on that page. Provider-stated D-PHY high-speed receiver rates are 80 Mbps to 1500 Mbps per lane without calibration, 1500 Mbps to 2500 Mbps with skew calibration, and 2500 Mbps to 4500 Mbps with equalization. C-PHY high-speed rates are stated from 182 Mbps (80 Msps) to 6840 Mbps (3 Gsps) per lane. Deliverables listed include Verilog HDL, a user guide, synthesis scripts, and a Verilog test suite. Confirm CSI-2 revision, D-PHY or C-PHY pairing, and lane count. Do not substitute the CSI-2 transmitter or a PHY for this receiver listing.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    CSI-2 receiver

Lifecycle and categories

Solution categories
MIPI IP
Supported versions
MIPI CSI-2 v2.1
Compatibility
The receiver page says the core can use either D-PHY or C-PHY by configuration. That statement does not include a PHY as part of this listing. Arasan’s D-PHY and C-PHY products remain separate. Source

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