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Arasan MIPI D-PHY 1.2 Analog Transceiver IP

The MIPI D-PHY Analog Transceiver product page reviewed on 12 November 2026 states that the core is fully compliant with the D-PHY specification version 1.2 and supports MIPI CSI-2 and DSI protocols.

Solution category: MIPI IP
Offering type: Product

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Overview

CSI-2 and DSI controllers are separate products.

It describes a universal PHY that can be configured as a transmitter, receiver, or transceiver, with a typical configuration of one clock lane and one to four data lanes. High-speed mode is stated from 80 Mbps to 1500 Mbps per lane without deskew calibration and up to 2500 Mbps with deskew calibration. Low-power mode is stated at 10 Mbps. The page names a PPI interface, master or slave configuration, unidirectional or bidirectional lane operation, and deliverables that include GDS-II, LVS netlist, LEF, timing models, and a process-specific integration guide. It says the IP is available in various foundry processes and does not name a single foundry on that page. Confirm transmitter, receiver, or transceiver configuration, lane count, and process node with Arasan.

Technical capabilities

Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
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MIPI D-PHY
Numbered specification: MIPI D-PHY v1.2
MIPI D-PHY v1.2 is named for this product on the reviewed page.

Lifecycle and categories

Lifecycle stages: Interface and connectivity IP
Solution categories: MIPI IP
Supported versions: MIPI D-PHY v1.2
Compatibility: The page says the D-PHY supports CSI-2 and DSI. Pairing a controller from this portfolio or another vendor is a separate configuration choice. Controllers are not included in this listing. Source