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Mixel MIPI D-PHY (MXL-DPHY)

The MIPI D-PHY product page reviewed on 12 November 2026 describes MXL-DPHY as a high-frequency, low-power, source-synchronous physical layer compliant with the MIPI Alliance Standard for D-PHY.

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Overview

It states compliance with MIPI D-PHY Specification v3.5 with backward compatibility for v3.0, v2.5, v2.1, v1.2, and v1.1. The page says the PHY is partitioned into a digital CIL module and a mixed-signal module, provided as Soft IP views (RTL and STA constraints) plus Hard IP views (GDSII/CDL/LEF/LIB), and uses the PHY-Protocol Interface (PPI) toward protocol layers. It states support for CSI-2, DSI, and DSI-2, high-speed rates from 80 Mbps to 6.5 Gbps, and low-power mode at 10 Mbps. Configurations named include Universal Lane, transmit-only, receive-only, DSI, CSI, TX+, and RX+. A production-ready offering table lists foundry/node SKUs (for example TSMC, GlobalFoundries, UMC, Samsung, SMIC, Tower). Controllers remain separate products in Mixel’s MIPI portfolio. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • PHY IP

    Physical-layer IP. Controllers are separate listings unless the page states a bundle.

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    MIPI D-PHY

Lifecycle and categories

Solution categories
MIPI IP
Supported versions
MIPI D-PHY v3.5 (backward compatible with v3.0, v2.5, v2.1, v1.2, v1.1)
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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