
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The reviewed page states CSI-2 v2.1 support.
CSI-2 v2.1 receiver controller that unpacks incoming camera streams.
The RX core decodes incoming sensor packets and forwards payloads to pixel-stream interfaces. The D-PHY is not included. Silicon Showcase™ reviewed the page on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.
Published as design IP
Licensable CSI-2 receiver design IP.
Controller IP
Digital receiver controller. The analog PHY is separate.
Finder function
CSI-2 receiver
Recorded aliases
Cadence CSI-2 Receiver; Cadence CSI2RX
Synopsys MIPI CSI-2 Controller IP is DesignWare controller IP for the link between an image processor and a CSI-2 image sensor. It is licensable controller IP, not a camera chip and not the C-PHY or D-PHY.
View solutionSynopsys MIPI DSI/DSI-2 Host Controller IP is the display-output host role. The PHY, including C-PHY or D-PHY, is separate. This listing is not a MIPI CSI-2 camera receiver, not a GPU, and not a PHY-only block.
View solutionT2M MIPI DSI Tx v1.2 Controller IP is licensable display-serial-interface controller soft IP. The official product page states compliance with MIPI DSI specification v1.2 and lists configurable RTL deliverables.
View solutionArasan MIPI CSI-2 v2.1 Receiver IP is licensable camera receiver controller IP. It is the CSI-2 v2.1 receiver offering. The CSI-2 transmitter and the analog PHY are separate products on Arasan’s MIPI pages.
View solutionArasan MIPI D-PHY 1.2 Analog Transceiver IP is licensable PHY IP. The page says it can be configured as a transmitter, receiver, or transceiver, with high-speed operation up to 2.5 Gb/s per lane with deskew calibration. CSI-2 and DSI controllers are separate products.
View solution
