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Public source

T2M MIPI DSI Transmitter v1.2 Controller IP Core

The MIPI DSI Transmitter v1.2 Controller IP Core page reviewed on 12 November 2026 describes a DSI transmitter controller for host-to-display links.

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Overview

T2M MIPI DSI Tx v1.2 Controller IP is licensable display-serial-interface controller soft IP.

It states compliance with mipi_DSI_specification_v1-2.pdf and programmable 1, 2, or 4 data-lane configuration. Documented features include forward and reverse LP communication on 1 lane; ECC and CRC generation; short and long packets; up to 4 virtual channels; pixel interfaces of 16/18/24/36 bits per pixel; continuous and non-continuous clock modes; Command and Video Mode (burst and non-burst); EOTP enable/disable; stereoscopic image data; and optional VESA Display Stream Compression V1.1 encoder support. Deliverables listed include configurable RTL code, HDL test bench and behavioral models, test cases, protocol checkers, synthesis shell, and documentation. The page labels the offering silicon-proven IP. Official page confirms silicon-proven DSI TX controller with RTL deliverables; city Kissing from GmbH registry address.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    MIPI DSI TX controller

  • Numbered specification: MIPI DSI v1.2

    MIPI DSI v1.2 is named for this product on the reviewed page.

Lifecycle and categories

Solution categories
MIPI IP
Supported versions
MIPI DSI v1.2
Compatibility
Configurable 1/2/4-lane D-PHY-oriented CIL modes stated; PHY itself is separate. Source

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