
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Synopsys page reviewed on 26 October 2026 describes MIPI CSI-2 host and device controller IP.
It is licensable controller IP, not a camera chip and not the C-PHY or D-PHY.
It says the controllers implement protocol functions in the MIPI CSI-2 specification and provide a high-speed serial interface between an application or image processor and image sensors. Synopsys states configuration up to 8 data lanes or 3 trios, transfers from 80 Mb/s in low-power mode to 3.5 Gs/s per trio and 4.5 Gbps per lane, and a PHY Protocol Interface to C-PHY and D-PHY. Those rates are provider-stated and were not remeasured. The page says the controllers are ASIL B Ready ISO 26262 certified. It also says the host controllers can be used with a separate MIPI CSE 2.0 security module. The page does not name a numbered CSI-2 revision, a foundry process, or a license grant. A C-PHY or D-PHY on the same portfolio page is not copied onto this controller listing.
Licensable design IP. CSI-2 v2.1 receiver controller that unpacks incoming camera streams.
View solutionT2M MIPI DSI Tx v1.2 Controller IP is licensable display-serial-interface controller soft IP. The official product page states compliance with MIPI DSI specification v1.2 and lists configurable RTL deliverables.
View solutionArasan MIPI CSI-2 v2.1 Receiver IP is licensable camera receiver controller IP. It is the CSI-2 v2.1 receiver offering. The CSI-2 transmitter and the analog PHY are separate products on Arasan’s MIPI pages.
View solutionArasan MIPI D-PHY 1.2 Analog Transceiver IP is licensable PHY IP. The page says it can be configured as a transmitter, receiver, or transceiver, with high-speed operation up to 2.5 Gb/s per lane with deskew calibration. CSI-2 and DSI controllers are separate products.
View solutionLicensable design IP. MIPI D-PHY with documented TX-only, RX-only, and combined configurations.
View solution
