
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The DisplayPort 1.1a Transmitter page reviewed on 12 November 2026 describes an IP core fully compliant with DisplayPort 1.1a with HDCP content protection, providing signal requirements for a DisplayPort source receptacle (HDMI mode requires an external DisplayPort-to-HDMI converter).
Analogix DisplayPort 1.1a Transmitter is licensable DisplayPort source IP. The official page states DisplayPort 1.1a compliance with HDCP and a 4-lane main link at 2.7/1.62 Gbps per lane.
Video features include EIA/CEA-861D timing/info-frames, VESA DMT and CVT timings, deep color up to 36 bpp, and BIST. Audio features include S/PDIF and I2S inputs supporting PCM/Dolby Digital/DTS, IEC60958/IEC61937 compatibility, and sampling rates 32–192 kHz. Other features include a main link of 4 physical lanes at 2.7/1.62 Gbps/lane and an APB 3.0 configuration/status interface. A product brief PDF is offered. Category mapped to serdes-ip as the closest allowed high-speed serial interface ID (no dedicated DisplayPort category in the allowed set).
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
DisplayPort transmitter
Numbered specification: DisplayPort 1.1a with HDCP
DisplayPort 1.1a with HDCP is named for this product on the reviewed page.
Recorded aliases
Analogix DP 1.1a Transmitter; DisplayPort 1.1a Transmitter IP
Analog Bits SerDes is licensable multi-protocol enterprise-class SerDes IP. The official page states PCIe Gen 3/4/5-class SerDes with silicon tape-outs in 8 nm, 7 nm, and 5 nm and customization for customer requirements.
View solutionCredo SerDes is high-speed serializer/deserializer silicon and IP for data-center and AI interconnect, not a compute accelerator architecture.
View solutionEuresys Vision Standard IP Cores are licensable FPGA IP for GigE Vision, USB3 Vision, and CoaXPress. The official IP Cores page states compact, customizable cores with reference designs for AMD, Intel, and Microchip PolarFire FPGAs.
View solutionFermionIC publishes multi-protocol SERDES semiconductor IP for high-speed chip-to-chip and system connectivity across advanced digital interfaces.
View solutionInCirT Broadband Data Conversion Silicon IP is licensable mixed-signal converter IP. The official site states breakthrough broadband data-conversion technology as silicon IP for satellite, radar, mmWave 5G/6G, Wi-Fi, and test-and-measurement applications.
View solutionKandou Glasswing is licensable ultra-short-reach (USR) chiplet interconnect SerDes IP using CNRZ-5 Chord signaling. The official product page states 500 Gbit/s bidirectional throughput SKUs with GlobalFoundries 12LP availability and no-interposer 150 µm bump pitch.
View solution
