
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Glasswing Chiplet Interconnect IP page reviewed on 12 November 2026 describes Glasswing as chip-to-chip link IP using CNRZ-5 Chord signaling for more bits with lower power and fewer pins.
Kandou Glasswing is licensable ultra-short-reach (USR) chiplet interconnect SerDes IP using CNRZ-5 Chord signaling.
Marketing claims include USR SerDes proven in low-cost silicon, about 1 Tbps bandwidth under one watt class efficiency, tiling for terabit die-to-die bandwidth, beachfront bandwidth of 208 Gbit/s/mm die edge, 6 dB insertion-loss budget (40+ mm on GZ-41 substrate), standard 150 µm bump pitch without interposer, low fixed latency, native BER 1E-15 with optional FEC to below 1E-20, PRBS/loopback, protocol-agnostic operation, and built-in EyeScope diagnostics. Product SKU GW12-500-USR lists peak throughput 500 Gbits/s, bandwidth density 208.3 Gbit/s per mm of die edge, CNRZ-5 on 6 wires, and process GlobalFoundries 12LP. Feature list also states 500 Gbits/s bidirectional throughput and 1.04 pJ/bit or 1 Tbit/s per Watt efficiency figures. Official product page confirms Glasswing USR SerDes chiplet interconnect IP with named SKU and foundry node.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
PHY IP
Physical-layer IP. Controllers are separate listings unless the page states a bundle.
Finder function
USR chiplet SerDes
Numbered specification: GW12-500-USR on GF 12LP
GW12-500-USR on GF 12LP is named for this product on the reviewed page.
Analog Bits SerDes is licensable multi-protocol enterprise-class SerDes IP. The official page states PCIe Gen 3/4/5-class SerDes with silicon tape-outs in 8 nm, 7 nm, and 5 nm and customization for customer requirements.
View solutionAnalogix DisplayPort 1.1a Transmitter is licensable DisplayPort source IP. The official page states DisplayPort 1.1a compliance with HDCP and a 4-lane main link at 2.7/1.62 Gbps per lane.
View solutionCredo SerDes is high-speed serializer/deserializer silicon and IP for data-center and AI interconnect, not a compute accelerator architecture.
View solutionEuresys Vision Standard IP Cores are licensable FPGA IP for GigE Vision, USB3 Vision, and CoaXPress. The official IP Cores page states compact, customizable cores with reference designs for AMD, Intel, and Microchip PolarFire FPGAs.
View solutionFermionIC publishes multi-protocol SERDES semiconductor IP for high-speed chip-to-chip and system connectivity across advanced digital interfaces.
View solutionInCirT Broadband Data Conversion Silicon IP is licensable mixed-signal converter IP. The official site states breakthrough broadband data-conversion technology as silicon IP for satellite, radar, mmWave 5G/6G, Wi-Fi, and test-and-measurement applications.
View solution
