
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
Credo SerDes is a publicly described Credo Technology connectivity offering.
Credo SerDes is high-speed serializer/deserializer silicon and IP for data-center and AI interconnect, not a compute accelerator architecture.
Official Credo pages present SerDes design as the company’s core connectivity silicon advantage, including high-speed DSP SerDes for data-center links. This listing records the SerDes platform rather than every AEC or optical DSP SKU.
Analog Bits SerDes is licensable multi-protocol enterprise-class SerDes IP. The official page states PCIe Gen 3/4/5-class SerDes with silicon tape-outs in 8 nm, 7 nm, and 5 nm and customization for customer requirements.
View solutionAnalogix DisplayPort 1.1a Transmitter is licensable DisplayPort source IP. The official page states DisplayPort 1.1a compliance with HDCP and a 4-lane main link at 2.7/1.62 Gbps per lane.
View solutionEuresys Vision Standard IP Cores are licensable FPGA IP for GigE Vision, USB3 Vision, and CoaXPress. The official IP Cores page states compact, customizable cores with reference designs for AMD, Intel, and Microchip PolarFire FPGAs.
View solutionFermionIC publishes multi-protocol SERDES semiconductor IP for high-speed chip-to-chip and system connectivity across advanced digital interfaces.
View solutionInCirT Broadband Data Conversion Silicon IP is licensable mixed-signal converter IP. The official site states breakthrough broadband data-conversion technology as silicon IP for satellite, radar, mmWave 5G/6G, Wi-Fi, and test-and-measurement applications.
View solutionKandou Glasswing is licensable ultra-short-reach (USR) chiplet interconnect SerDes IP using CNRZ-5 Chord signaling. The official product page states 500 Gbit/s bidirectional throughput SKUs with GlobalFoundries 12LP availability and no-interposer 150 µm bump pitch.
View solution