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Analog Bits Multi-protocol PCIe-class SerDes IP

The SerDes product page reviewed on 12 November 2026 describes lowest-power PCIe Gen 3/4/5-class SerDes customizable to unique requirements.

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Overview

It states silicon taped out in 8 nm, 7 nm, and 5 nm, and offers 32 Gbps multi-protocol, enterprise-class PCIe Gen 4/5 SerDes from which Analog Bits can customize. Named attributes include multiprotocol support (PCIe, SAS, SATA, HMC, USB…), unlimited lane count with multiple data rates, flexible placement anywhere on the SoC, and claims of half power and smallest die area versus competing alternatives. SOC application areas listed include FPGA, consumer cables, mobile computing, and SSD. Headquarters address 920 Stewart Drive, Suite 200, Sunnyvale, CA 94085 is printed on the page.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • PHY IP

    Physical-layer IP. Controllers are separate listings unless the page states a bundle.

  • Finder function

    PCIe-class multi-protocol SerDes

  • Numbered specification: 32 Gbps multi-protocol SerDes stated

    32 Gbps multi-protocol SerDes stated is named for this product on the reviewed page.

  • Recorded aliases

    Analog Bits SerDes; Analog Bits PCIe Gen4/5 SerDes

Lifecycle and categories

Solution categories
SerDes IP
Supported versions
PCIe Gen 3/4/5-class; 32 Gbps multi-protocol SerDes stated
Compatibility
8/7/5 nm tape-outs stated; multiprotocol PCIe/SAS/SATA/HMC/USB customization. Source

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