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Public source

Attopsemi I-fuse OTP IP

The I-fuse technology page reviewed on 12 November 2026 describes I-fuse as an OTP programming mechanism modeled by heat generation/dissipation and electro-migration, contrasting non-explosive fuse behavior with conventional explosive fuses.

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Overview

Core competence claims include foundry independence (no extra mask/step or hidden layers), programming of poly/metal-gate/metal fuse (not MOS), small size without charge pumps (~1/10 eFuse size stated), low program voltage at core/I/O (1.1/1.8 V), short program time, low read voltage (0.4 V sub-VDD readable), ~1 µA read current, wide temperature (−55–150°C and beyond), high reliability (<1 ppb natural defect; 300°C HTS pass stated), and full testability via Concurrent Low-Voltage Write/Read (CLVWR) soft-program techniques. The page positions Attopsemi as offering optimal OTP design with special I-fuse circuit design service.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    OTP / I-fuse

  • Numbered specification: I-fuse OTP (foundry-independent

    I-fuse OTP (foundry-independent is named for this product on the reviewed page.

  • Numbered specification: voltage/temp ranges stated on page)

    voltage/temp ranges stated on page) is named for this product on the reviewed page.

  • Recorded aliases

    I-fuse; Attopsemi OTP; I-fuse OTP

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Embedded Memory IP
Supported versions
I-fuse OTP (foundry-independent; voltage/temp ranges stated on page)
Compatibility
Foundry-independent; no extra mask/step per page. Source

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