GUC HBM4E PHY and Controller IP

Licensable HBM4E PHY and controller IP, published as one combined interface. GUC says it is design-ready, states speeds up to 16 Gbps, and says the PHY has taped out on TSMC N2P with CoWoS-L. GUC’s silicon-proven statement for its earlier HBM4 IP is not recorded here.

GUC says the IP is design-ready and has been adopted in customer AI ASICs. The adoption claim was not matched to a named customer chip. Tape-out is a manufacturing handoff of that PHY.

GUC states data transfer speeds up to 16 Gbps across the operating conditions it has signed off. That is a stated maximum, not a pin rate confirmed for every width and package. The announcement says this work builds on GUC’s silicon-proven 12 Gbps HBM4 IP on TSMC N3P. That earlier status stays with the earlier HBM4 IP. It is not copied onto HBM4E.

The same announcement describes a face-up HBM4E variant for a bottom die in TSMC SoIC-X, with TSVs for signal pull-out and feedthrough power. It is not a second catalog row. GUC also says the IP includes proteanTecs interconnect monitoring. No separate monitoring product is listed from that sentence. GUC’s advanced-packaging design service remains a different listing.