Silicon Showcase⁠™

Your shortlist

Nothing saved yet.

Save a solution from IP Finder, a solution listing, a solution page, or a provider’s solutions to compare it here.

Saved in this browser. Information is based on published sources. Confirm suitability and configuration with the provider.

Public source

SkyeChip HBM3/3E PHY & Controller

The SkyeChip IP Solutions page reviewed on 12 November 2026 describes an HBM3/3E PHY & Controller as a bandwidth- and area-optimized low-power memory interface for AI, HPC, data centers, and networking, conforming to HBM3 (JESD238A).

View Official Source (opens in a new tab)Find IP for your application

Overview

SkyeChip HBM3/3E PHY & Controller is a licensable one-stop memory-interface IP solution.

Stated features include average random efficiency greater than 85%, up to 6400 MT/s for HBM3 and up to 9600 MT/s for HBM3E, DFI 5.1 compatibility, programmable interface training, IEEE 1500 support, up to 32 Gb density per die, up to 16H stacks, and 2.5D/3D packaging support. The same page lists related DDR5/4, LPDDR5/5X, coherent/non-coherent NoC, and UCIe PHY & Controller products. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    HBM3 PHY & controller

  • Numbered specification: HBM3 (JESD238A)

    HBM3 (JESD238A) is named for this product on the reviewed page.

  • Numbered specification: HBM3E rates stated up to 9600 MT/s

    HBM3E rates stated up to 9600 MT/s is named for this product on the reviewed page.

  • Recorded aliases

    SkyeChip HBM3 IP; SkyeChip HBM3E PHY

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
DDR & HBM IP
Supported versions
HBM3 (JESD238A); HBM3E rates stated up to 9600 MT/s
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

Related solutions

Cadence LPDDR5/4X PHY IP for TSMC N7

DDR & HBM IP

Licensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.

View solution

Dolphin Technology Hardened Combo DDR/LPDDR PHY IP

DDR & HBM IP

Dolphin Technology hardened Combo DDR/LPDDR PHY is licensable hard PHY IP. The official page states a silicon-proven combo PHY supporting DDR4/3/2 and LPDDR5/4x/4/3/2 up to 4266 Mbps with DFI 4.0 compliance.

View solution

GUC HBM4E PHY and Controller IP

DDR & HBM IP

Licensable HBM4E PHY and controller IP, published as one combined interface. GUC says it is design-ready, states speeds up to 16 Gbps, and says the PHY has taped out on TSMC N2P with CoWoS-L. GUC’s silicon-proven statement for its earlier HBM4 IP is not recorded here.

View solution

OPENEDGES OPHY

DDR & HBM IP

OPENEDGES OPHY is DDR PHY IP. The memory controller is OMC, a separate product. Process availability: LPDDR6/5X PHY: 4nm. LPDDR5/4X/4 PHY: 14nm. LPDDR4X/4 PHY: 12nm, 14nm, 16nm. LPDDR3/DDR3 PHY: 28nm. DDR5 PHY: 5nm. LPDDR5X/5/4X/4 PHY: 5nm, 7/6nm, 12nm, 16nm. LPDDR5/4 PHY: 5nm, 8nm. LPDDR/4 PHY: 22nm. LPDDR4/3/DDR4/3 PHY: 28nm. A node belongs only to the row that names it. The LPDDR/4 label is not recorded as LPDDR4. LPDDR6 up to 14400 Mbps is marked Planning.

View solution

Synopsys DDR5/4 PHY IP

DDR & HBM IP

Licensable DDR5 and DDR4 PHY IP. The page documents up to 8400 Mb/s, DFI 5.0, and a hard PHY. A memory controller is not included.

View solution

Synopsys HBM Interface IP

DDR & HBM IP

Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.

View solution

Related events

Explore promotion options