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OPENEDGES OPHY

The OPHY page describes hard and soft DDR PHY IP.

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Overview

The memory controller is OMC, a separate product. LPDDR3/DDR3 PHY: 28nm. LPDDR/4 PHY: 22nm. LPDDR6 up to 14400 Mbps is marked Planning.

Key features name JEDEC LPDDR6/5X/5/4X/4 and DDR5, a DFI interface without a DFI version, LPDDR6 data widths of 24 or 48 bits per channel, and LPDDR5x/5/4 data widths of 16 or 32 bits per channel. Stated rates are up to 8533 Mbps for LPDDR5X and up to 4266 Mbps for LPDDR4X. The page also lists up to four ranks and up to four frequency set points. Deliverables include GDSII, LEF, LVS, timing models, Verilog behavior models, encrypted RTL, synthesis and STA constraints, example test benches, and a PHY technical reference manual. The memory subsystem page describes OPHY as the PHY used with OMC and OIC. Confirm the memory standard and the process node on the same availability row. The LPDDR/4 row is not a confirmed LPDDR4 listing. Foundry, DFI version, and the planned LPDDR6 rate are not recorded as available.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    DDR PHY

  • Numbered specification: LPDDR6

    LPDDR6 is named for this product on the reviewed page.

  • Numbered specification: LPDDR5X

    LPDDR5X is named for this product on the reviewed page.

  • Numbered specification: LPDDR5

    LPDDR5 is named for this product on the reviewed page.

  • Numbered specification: LPDDR4X

    LPDDR4X is named for this product on the reviewed page.

  • Numbered specification: LPDDR4

    LPDDR4 is named for this product on the reviewed page.

  • Numbered specification: DDR5

    DDR5 is named for this product on the reviewed page.

  • Numbered specification: LPDDR3

    LPDDR3 is named for this product on the reviewed page.

  • Numbered specification: DDR4

    DDR4 is named for this product on the reviewed page.

  • Numbered specification: DDR3

    DDR3 is named for this product on the reviewed page.

  • Process availability

    LPDDR6/5X PHY: 4nm. LPDDR5/4X/4 PHY: 14nm. LPDDR4X/4 PHY: 12nm, 14nm, 16nm. LPDDR3/DDR3 PHY: 28nm. DDR5 PHY: 5nm. LPDDR5X/5/4X/4 PHY: 5nm, 7/6nm, 12nm, 16nm. LPDDR5/4 PHY: 5nm, 8nm. LPDDR/4 PHY: 22nm. LPDDR4/3/DDR4/3 PHY: 28nm.

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
DDR & HBM IP
Supported versions
LPDDR6; LPDDR5X; LPDDR5; LPDDR4X; LPDDR4; DDR5; LPDDR3; DDR4; DDR3
Compatibility
A process node applies only to the OPHY availability row that names it. The memory subsystem page describes OPHY with OMC and OIC and does not show that every row is paired or licensed with those products. Source

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