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Dolphin Technology Hardened Combo DDR/LPDDR PHY IP

The DDR PHY page reviewed on 12 November 2026 describes Dolphin’s hardened DDR4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP as a silicon-proven Combo PHY supporting speeds up to 4266 Mbps.

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Overview

It states full compliance with the DFI 4.0 specification and features including slew rate control, per-bit de-skew, gate training, read and write leveling, and built-in self test (BIST). The page says the PHY is optimized to provide a complete solution when combined with Dolphin’s DDRx and LPDDRx SDRAM Memory Controller IP (controllers are separate products). Technology-level availability is referenced via an on-page chart link.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • PHY IP

    Physical-layer IP. Controllers are separate listings unless the page states a bundle.

  • Finder function

    DDR/LPDDR PHY

  • Numbered specification: DDR4/3/2

    DDR4/3/2 is named for this product on the reviewed page.

  • Numbered specification: DFI 4.0

    DFI 4.0 is named for this product on the reviewed page.

  • Recorded aliases

    Dolphin Combo DDR PHY; Dolphin LPDDR5 PHY

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
DDR & HBM IP
Supported versions
DDR4/3/2; LPDDR5/4x/4/3/2; DFI 4.0; up to 4266 Mbps
Compatibility
DFI 4.0 toward Dolphin DDRx/LPDDRx controllers; process SKUs via on-page chart. Source

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DDR & HBM IP

Licensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.

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GUC HBM4E PHY and Controller IP

DDR & HBM IP

Licensable HBM4E PHY and controller IP, published as one combined interface. GUC says it is design-ready, states speeds up to 16 Gbps, and says the PHY has taped out on TSMC N2P with CoWoS-L. GUC’s silicon-proven statement for its earlier HBM4 IP is not recorded here.

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SkyeChip HBM3/3E PHY & Controller

DDR & HBM IP

SkyeChip HBM3/3E PHY & Controller is a licensable one-stop memory-interface IP solution. The official IP Solutions page states JEDEC HBM3 (JESD238A) conformance with rates up to 6400 MT/s (HBM3) and 9600 MT/s (HBM3E) and a DFI 5.1 PHY-to-controller interface.

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Synopsys DDR5/4 PHY IP

DDR & HBM IP

Licensable DDR5 and DDR4 PHY IP. The page documents up to 8400 Mb/s, DFI 5.0, and a hard PHY. A memory controller is not included.

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True Circuits PLL / DLL / DDR PHY Hard Macros

DDR & HBM IP

True Circuits PLL, DLL, and DDR PHY hard macros are licensable mixed-signal timing and memory-interface IP. The official product matrix links datasheets for standard hard macros across TSMC nodes with DDR rates up to 6400 MT/s on advanced nodes.

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OPENEDGES OPHY

DDR & HBM IP

OPENEDGES OPHY is DDR PHY IP. The memory controller is OMC, a separate product. Process availability: LPDDR6/5X PHY: 4nm. LPDDR5/4X/4 PHY: 14nm. LPDDR4X/4 PHY: 12nm, 14nm, 16nm. LPDDR3/DDR3 PHY: 28nm. DDR5 PHY: 5nm. LPDDR5X/5/4X/4 PHY: 5nm, 7/6nm, 12nm, 16nm. LPDDR5/4 PHY: 5nm, 8nm. LPDDR/4 PHY: 22nm. LPDDR4/3/DDR4/3 PHY: 28nm. A node belongs only to the row that names it. The LPDDR/4 label is not recorded as LPDDR4. LPDDR6 up to 14400 Mbps is marked Planning.

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