Public source

Cadence LPDDR5/4X PHY IP for TSMC N7

The Cadence datasheet is dated April 2020.

Solution category: DDR & HBM IP
Offering type: Product

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Overview

It identifies LPDDR5 and LPDDR4X, TSMC N7, a 6400 Mb/s operating point, and DFI up to 5.0. Physical deliverables described include GDSII and LEF models. The controller is a separate product, and no pairing is verified. Current delivery of this process variant requires provider confirmation. Silicon Showcase⁠™ reviewed the datasheet on 2 November 2026. Pricing and license terms remain unstated.

Technical capabilities

Published as design IP
Licensable LPDDR PHY design IP for the documented TSMC N7 variant.
PHY IP
DRAM PHY. The memory controller is a separate product.
Finder function
memory PHY

Lifecycle and categories

Lifecycle stages: Memory and subsystem IP
Solution categories: DDR & HBM IP
Supported versions: LPDDR5, LPDDR4X
Compatibility: Pricing, licensing, and configuration availability require provider confirmation. Source

Official resources

Cadence LPDDR5/4X PHY IP for TSMC N7 (opens in a new tab)

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