Memory & Subsystem IP

DDR & HBM IP

PHY and related interface IP for DDR or HBM. A mention that a product is distinct from UCIe does not make it a die-to-die listing.

Showing 1–9 of 9 solutions.

Cadence LPDDR5/4X PHY IP for TSMC N7
DDR & HBM IP
Licensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.
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Dolphin Technology Hardened Combo DDR/LPDDR PHY IP
DDR & HBM IP
Dolphin Technology hardened Combo DDR/LPDDR PHY is licensable hard PHY IP. The official page states a silicon-proven combo PHY supporting DDR4/3/2 and LPDDR5/4x/4/3/2 up to 4266 Mbps with DFI 4.0 compliance.
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GUC HBM4E PHY and Controller IP
DDR & HBM IP
Licensable HBM4E PHY and controller IP, published as one combined interface. GUC says it is design-ready, states speeds up to 16 Gbps, and says the PHY has taped out on TSMC N2P with CoWoS-L. GUC’s silicon-proven statement for its earlier HBM4 IP is not recorded here.
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OPENEDGES OPHY
DDR & HBM IP
OPENEDGES OPHY is DDR PHY IP. The memory controller is OMC, a separate product. Process availability: LPDDR6/5X PHY: 4nm. LPDDR5/4X/4 PHY: 14nm. LPDDR4X/4 PHY: 12nm, 14nm, 16nm. LPDDR3/DDR3 PHY: 28nm. DDR5 PHY: 5nm. LPDDR5X/5/4X/4 PHY: 5nm, 7/6nm, 12nm, 16nm. LPDDR5/4 PHY: 5nm, 8nm. LPDDR/4 PHY: 22nm. LPDDR4/3/DDR4/3 PHY: 28nm. A node belongs only to the row that names it. The LPDDR/4 label is not recorded as LPDDR4. LPDDR6 up to 14400 Mbps is marked Planning.
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SkyeChip HBM3/3E PHY & Controller
DDR & HBM IP
SkyeChip HBM3/3E PHY & Controller is a licensable one-stop memory-interface IP solution. The official IP Solutions page states JEDEC HBM3 (JESD238A) conformance with rates up to 6400 MT/s (HBM3) and 9600 MT/s (HBM3E) and a DFI 5.1 PHY-to-controller interface.
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Synopsys DDR5/4 PHY IP
DDR & HBM IP
Licensable DDR5 and DDR4 PHY IP. The page documents up to 8400 Mb/s, DFI 5.0, and a hard PHY. A memory controller is not included.
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Synopsys HBM Interface IP
DDR & HBM IP
Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.
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True Circuits PLL / DLL / DDR PHY Hard MacrosTrue Circuits, Inc.
DDR & HBM IP
True Circuits PLL, DLL, and DDR PHY hard macros are licensable mixed-signal timing and memory-interface IP. The official product matrix links datasheets for standard hard macros across TSMC nodes with DDR rates up to 6400 MT/s on advanced nodes.
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Uniquify High-Speed Adaptive DDR Interface IP
DDR & HBM IP
Uniquify Adaptive DDR Interface is licensable DDR/LPDDR/HBM memory-interface IP. The official IP page states patented adaptive technologies for PVT variation, covering DDR3/4/5, LPDDR3/4/5, and HBM across foundries from 65 nm to 7 nm.
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