
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Uniquify IP page reviewed on 12 November 2026 describes a High-Speed Adaptive DDR Interface as the only DDR system with patented adaptive technologies adaptable to PVT and system variations, addressing both high performance and low power.
The official IP page states patented adaptive technologies for PVT variation, covering DDR3/4/5, LPDDR3/4/5, and HBM across foundries from 65 nm to 7 nm.
Supported standards listed include DDR3/4/5, LPDDR3/4/5, and HBM. The page claims 24 US patents granted since 2006 in DDR interface technology and describes Self Calibrating Logic (SCL), automatic bit-to-bit skew reduction (ABC/DABC), and foundry/node coverage from 65 nm to 7 nm. Related IP themes on the same page include high-speed SerDes, video display technology, and Edge AI Neural Net 2.0. Confirm the exact revision, role, and deliverables on the current provider page before integration.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
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Adaptive DDR interface
Numbered specification: DDR3/4/5
DDR3/4/5 is named for this product on the reviewed page.
Numbered specification: LPDDR3/4/5
LPDDR3/4/5 is named for this product on the reviewed page.
Numbered specification: HBM*
HBM* is named for this product on the reviewed page.
Recorded aliases
Uniquify DDR IP; Uniquify Adaptive DDR
Licensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.
View solutionDolphin Technology hardened Combo DDR/LPDDR PHY is licensable hard PHY IP. The official page states a silicon-proven combo PHY supporting DDR4/3/2 and LPDDR5/4x/4/3/2 up to 4266 Mbps with DFI 4.0 compliance.
View solutionLicensable HBM4E PHY and controller IP, published as one combined interface. GUC says it is design-ready, states speeds up to 16 Gbps, and says the PHY has taped out on TSMC N2P with CoWoS-L. GUC’s silicon-proven statement for its earlier HBM4 IP is not recorded here.
View solutionOPENEDGES OPHY is DDR PHY IP. The memory controller is OMC, a separate product. Process availability: LPDDR6/5X PHY: 4nm. LPDDR5/4X/4 PHY: 14nm. LPDDR4X/4 PHY: 12nm, 14nm, 16nm. LPDDR3/DDR3 PHY: 28nm. DDR5 PHY: 5nm. LPDDR5X/5/4X/4 PHY: 5nm, 7/6nm, 12nm, 16nm. LPDDR5/4 PHY: 5nm, 8nm. LPDDR/4 PHY: 22nm. LPDDR4/3/DDR4/3 PHY: 28nm. A node belongs only to the row that names it. The LPDDR/4 label is not recorded as LPDDR4. LPDDR6 up to 14400 Mbps is marked Planning.
View solutionSkyeChip HBM3/3E PHY & Controller is a licensable one-stop memory-interface IP solution. The official IP Solutions page states JEDEC HBM3 (JESD238A) conformance with rates up to 6400 MT/s (HBM3) and 9600 MT/s (HBM3E) and a DFI 5.1 PHY-to-controller interface.
View solutionLicensable DDR5 and DDR4 PHY IP. The page documents up to 8400 Mb/s, DFI 5.0, and a hard PHY. A memory controller is not included.
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