Memory & Subsystem IP

System Cache IP

Standalone last-level or system cache IP. This is not a DRAM controller, an OTP, or a die-to-die PHY.

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Embedded Memory IP
DDR & HBM IP
Memory Controllers
System Cache IP

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Arteris CodaCache Last-Level Cache IP
System Cache IP
Licensable standalone last-level cache IP for a non-coherent AXI4 interface. It is not a cache-coherent NoC, not a DDR controller, and not an OTP.
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