On-chip memory, external DRAM interfaces, and the controllers that sit above them. An interface PHY and a memory controller answer different questions.
IP-Maker IPM-NVMe_Device is licensable NVMe device controller IP for PCIe SSD designs. The official page states UNH-IOL NVM Express compliance and listing on the NVMe integrator’s list.
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Embedded flash technology for compatible chip processes and applications.
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IntelliProp IPP-NV186A-BR is licensable NVMe-to-SATA bridge RTL. The official page states hardware translation between NVMe host commands and SATA FIS for FPGA and ASIC.
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MLE NVMe Streamer is licensable full-accelerator NVMe host subsystem IP for FPGAs. The official page states CPU-less NVMe host operation over PCIe Gen1–Gen4 with production license offerings.
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eMemory NeoFuse is anti-fuse embedded OTP/PMTP silicon IP for logic process nodes, not a discrete memory product.
View solutionOPENEDGES OMC is DDR memory controller IP. The page delivers it as IP core RTL and says it schedules DRAM for an SoC. OPHY and OIC are separate products.
View solutionOPENEDGES OPHY is DDR PHY IP. The memory controller is OMC, a separate product. Process availability: LPDDR6/5X PHY: 4nm. LPDDR5/4X/4 PHY: 14nm. LPDDR4X/4 PHY: 12nm, 14nm, 16nm. LPDDR3/DDR3 PHY: 28nm. DDR5 PHY: 5nm. LPDDR5X/5/4X/4 PHY: 5nm, 7/6nm, 12nm, 16nm. LPDDR5/4 PHY: 5nm, 8nm. LPDDR/4 PHY: 22nm. LPDDR4/3/DDR4/3 PHY: 28nm. A node belongs only to the row that names it. The LPDDR/4 label is not recorded as LPDDR4. LPDDR6 up to 14400 Mbps is marked Planning.
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RAAAM GCRAM is licensable CMOS-compatible embedded memory IP positioned as a drop-in SRAM alternative. The official site claims up to 50% area reduction and up to 3× power reduction versus SRAM with no extra process steps.
View solutionLicensable HBM controller IP. The page documents an HBM3E pin rate of 9.6 Gb/s and an HBM3 pin rate of 8.4 Gb/s. A PHY is not included.
View solutionLicensable HBM4 controller IP. The page documents an HBM4 pin rate of 10 Gb/s. A PHY is not included.
View solutionRangduru DX-MRAM is positioned as licensable ultra-high-density logic OTP / AI memory IP. The official site brands Rangduru as a global leader in ultra-high-density, low-cost LOGIC OTP non-volatile memory solutions using DX-MRAM technology.
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SkyeChip HBM3/3E PHY & Controller is a licensable one-stop memory-interface IP solution. The official IP Solutions page states JEDEC HBM3 (JESD238A) conformance with rates up to 6400 MT/s (HBM3) and 9600 MT/s (HBM3E) and a DFI 5.1 PHY-to-controller interface.
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