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Public source

OPENEDGES OMC

The OMC page describes a DDR memory controller with a proprietary out-of-order scheduling algorithm, dual-PHY control for two DRAM channels from one OMC instance, and hardware-controlled dynamic DRAM frequency scaling.

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Overview

OPHY and OIC are separate products.

It states over 90% DRAM utilization for that scheduling algorithm. Configurable options on the page include channel DQ width (x4, x8, x16, x32, x64), up to five AXI manager ports, request and data queue depth, ActiveQoS with the OPENEDGES on-chip interconnect, and an optional AES-based memory encryptor. The page says OMC integrates with OPHY and OIC and also supports third-party DDR PHYs. Standards recorded here are the ones named in both the key-features list and the configurable-options list. The page says OMC achieved ISO 26262 and does not name an ASIL level. Deliverables listed are IP core RTL, a standalone simulation environment, management software, and IP documentation. Confirm the DRAM standard, PHY, and AXI configuration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    memory controller

  • Numbered specification: LPDDR6

    LPDDR6 is named for this product on the reviewed page.

  • Numbered specification: LPDDR5X

    LPDDR5X is named for this product on the reviewed page.

  • Numbered specification: LPDDR5

    LPDDR5 is named for this product on the reviewed page.

  • Numbered specification: LPDDR4X

    LPDDR4X is named for this product on the reviewed page.

  • Numbered specification: LPDDR4

    LPDDR4 is named for this product on the reviewed page.

  • Numbered specification: DDR4

    DDR4 is named for this product on the reviewed page.

  • Numbered specification: DDR3

    DDR3 is named for this product on the reviewed page.

  • Numbered specification: GDDR6

    GDDR6 is named for this product on the reviewed page.

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Memory Controllers
Supported versions
LPDDR6; LPDDR5X; LPDDR5; LPDDR4X; LPDDR4; DDR4; DDR3; GDDR6
Compatibility
The OMC page says it integrates with OPHY and OIC and supports third-party DDR PHYs. That statement does not identify a process node or confirm every DRAM standard. Source

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