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Cyclic Design BCH Error Correction IP

The Cyclic Design Verilog BCH ECC IP page reviewed on 12 November 2026 states highly optimized and flexible BCH Error Correction IP in Verilog for both SLC and MLC NAND flash applications, modular for high-performance and low-area use in SoC and FPGA architectures, including over 60 SVA assertions for integration checking.

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Overview

Named cores are G12 optimized for 256B correction blocks; G13/G13X for 512B; G14/G14X for 1KB; and G15 for 2KB correction blocks, sharing a common interface for drop-in upgrades and customization. Licensing options explicitly include single-instance, multiple-instance, and subscription licensing; detailed design data is provided under NDA. The home page frames the offering as an easy-to-integrate ECC solution so customers can retain existing NAND controller infrastructure while meeting rising ECC requirements. This listing uses the products URL as the primary official evidence URL.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    NAND BCH ECC engine

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Memory Controllers
Supported versions
BCH ECC cores G12 (256B), G13/G13X (512B), G14/G14X (1KB), G15 (2KB)
Compatibility
SoC and FPGA; Verilog; common interface across G12–G15 for upgrades. Source

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