On-chip memory, external DRAM interfaces, and the controllers that sit above them. An interface PHY and a memory controller answer different questions.
eMemory NeoEE is rewritable embedded EEPROM with up to 500000 program/erase cycles, low to medium density around 16 Kbits or less, and byte-write. The page states zero additional masking layers for this macro. That endurance and mask count do not transfer to NeoMTP or to NeoFlash.
View solutioneMemory NeoFlash is rewritable embedded flash. The listing says it needs 2 to 3 additional masks, on CMOS logic from about 180 nm to 22 nm, with over 100000 program/erase cycles. Density is per customer request. It is not a zero-mask embedded flash and it is not a discrete flash chip.
View solutioneMemory NeoMTP is rewritable single-poly embedded MTP. The listing states up to 1000 program/erase cycles and densities from about 16K to 512K bits. That endurance is not unlimited flash, not DRAM, and not one-time programmable storage.
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sureCore PowerMiser is licensable low-power SRAM IP. The official memory-products page states silicon realizations in 28 nm FDSOI, 28 nm HDC+, and 22 nm ULL bulk CMOS with compilers generating Verilog, LEF, and Liberty views.
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