sureCore PowerMiser Low-Power SRAM IP

It states realizations in 28 nm FDSOI as well as 28 nm HDC+ and 22 nm ULL bulk CMOS, with dynamic power savings exceeding 50% versus commercial instances on 28FDSOI over 0.7–1.2 V and leakage savings of about 21–38% at a stated 5–10% area penalty. Compilers support capacities up to 576 Kbit with word lengths up to 144 bits and mux factors 4/8/16, automatically generating datasheets, Verilog simulation, LEF, and Liberty models. Related products on the same page include PowerMiser Plus, EverOn ULV SRAM, MiniMiser register files, and CryoMem/CryoIP. Confirm the exact revision, role, and deliverables on the current provider page before integration.