
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The NVMe-to-SATA Bridge IP Core page reviewed on 12 November 2026 describes IPP-NV186A-BR as a silicon-proven hardware bridge that translates NVMe host commands into SATA protocol frames so legacy SATA SSDs/HDDs can attach to modern PCIe/NVMe architectures without host software changes.
It states compliance with NVMe Revision 1.3/1.4 and SATA 1.5/3.0/6.0 Gb/s (SATA 3.3). Features named include hardware SQ/CQ and SATA FIS translation, CPU offload of NVMe target registers and SATA host link state machines, automatic SATA speed negotiation, integrated DMA, decoupled clock domains via async FIFOs, SATA NCQ and Partial/Slumber power management, and delivery as synthesizable Verilog source or netlist for FPGA and ASIC. The page states U.S.-based engineering from Longmont, Colorado facilities. Official product page confirms licensable bridge RTL with stated NVMe/SATA revisions.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
NVMe-to-SATA bridge
Numbered specification: NVMe 1.3/1.4
NVMe 1.3/1.4 is named for this product on the reviewed page.
Recorded aliases
IPP-NV186A-BR; IntelliProp NVMe-to-SATA Bridge
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
View solutionLicensable design IP. DDR and LPDDR controller for LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
View solutionCyclic Design BCH ECC IP is licensable Verilog error-correction IP for SLC/MLC NAND flash controllers. The official products page lists G12–G15 core families by correction-block size with single-/multi-instance and subscription licensing options.
View solutionDigital Blocks AXI DMA Controller IP is licensable multi-channel scatter-gather DMA soft IP for AMBA AXI4 and AXI5. The official page details configurable/fixed-channel and high-throughput SystemVerilog RTL variants with full deliverables.
View solutionEureka EP530 is licensable synthesizable DDR SDRAM controller IP. The official product summary states ASIC/FPGA HDL delivery and standard DDR SDRAM device support.
View solution
