Interface IP for links off the chip and between dies. PCIe is one category. A protocol name is the category to check; it is not proof that a controller and a PHY are the same listing.
Licensable I3C 1.1 controller IP, part 76002, with an APB 3.0 host interface. The family brief lists advanced controller 76002, autonomous target 76005, and advanced target 76016 as separate products.
View solutionLicensable I3C 1.1 target IP, part 76016. The family brief lists it separately from advanced controller 76002 and autonomous target 76005.
View solution
Socionext IP Macros are a foundry/node-mapped lineup of interface and memory macros including PCIe RT/EP, DDR4/5, LPDDR4/5, HBM2/3, USB, Ethernet MAC, and MIPI DSI/CSI. The official Line-up of IP Macro page presents availability tables across 65 nm through 3 nm classes.
View solution
Soft Mixed Signal USB 2.0 PHY is licensable PHY transceiver IP. The official product page states a fully integrated Host/Device/OTG transceiver compliant with USB 2.0 and UTMI/UTMI+ interfaces.
View solution
StarIC SerDes/electro-photonic IP is licensable high-speed interconnect mixed-signal IP. The official site states silicon-proven SerDes, transceivers, TIAs/drivers, ADC/DAC, and photonic building blocks across advanced CMOS and silicon photonics platforms.
View solution
StreamDSP sFPDP-Gen3 is licensable high-speed serial communications FPGA IP. The official site lists VITA 17.1/17.3/Interlaken PHY serial communications cores for Xilinx, Intel, Lattice, and Microsemi FPGAs.
View solutionLicensable design IP. Digital Ethernet MAC for 1 Gb/s, 2.5 Gb/s, 5 Gb/s, and 10 Gb/s. The PHY is a separate product.
View solutionLicensable CXL controller IP. The product page documents device, host, switch, and dual-mode ports, and CXL 4.0 at 128 GT/s with backward compatibility to CXL 3.x, 2.0, and 1.x. The PCIe 5.0/CXL PHY, the IDE modules, and verification IP are not this listing.
View solutionLicensable controller IP for PCI Express. The page documents revisions 6.2, 6.1, 6.0.1, 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
View solutionLicensable design IP. Ethernet physical coding sublayer for 1 Gb/s, 2.5 Gb/s, 5 Gb/s, and 10 Gb/s. This is not an Ethernet MAC.
View solutionLicensable design IP. Digital Ethernet MAC with documented configurations at 1 Gb/s, 2.5 Gb/s, 5 Gb/s, 10 Gb/s, 25 Gb/s, 40 Gb/s, 50 Gb/s, and 100 Gb/s.
View solutionSynopsys MIPI CSI-2 Controller IP is DesignWare controller IP for the link between an image processor and a CSI-2 image sensor. It is licensable controller IP, not a camera chip and not the C-PHY or D-PHY.
View solutionExplore more
Search across providers and capabilities to discover more solutions for your SoC.
