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Public source

StreamDSP VITA 17.3 sFPDP-Gen3 IP Core

The StreamDSP home page reviewed on 12 November 2026 describes FPGA IP cores for high-speed serial, video, and DSP trusted by defense and aerospace engineers for 20+ years, supporting Xilinx, Intel, Lattice, and Microsemi device families.

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Overview

The official site lists VITA 17.1/17.3/Interlaken PHY serial communications cores for Xilinx, Intel, Lattice, and Microsemi FPGAs.

News highlights Lattice Avant G/X support for sFPDP-Gen3 (VITA 17.3) IP. Video processing (MIPI/video/ISP) and custom design consulting are also offered. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    sFPDP / serial communications

  • Numbered specification: VITA 17.1 / 17.3

    VITA 17.1 / 17.3 is named for this product on the reviewed page.

  • Numbered specification: Interlaken PHY also listed

    Interlaken PHY also listed is named for this product on the reviewed page.

  • Recorded aliases

    StreamDSP sFPDP; VITA 17.3 IP; sFPDP-Gen3

Lifecycle and categories

Solution categories
SerDes IP
Supported versions
VITA 17.1 / 17.3; Interlaken PHY also listed
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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