Services & Manufacturing
Assembly, substrates, and 2.5D/3D integration. A foundry process that mentions an interposer is still a foundry listing when the product is the wafer.
3D V-Cache stacks an L3 cache tile on a CPU core-complex die using copper-to-copper hybrid bonding and TSVs. Official AMD materials call it the first x86 true 3D die stack, with much higher interconnect density versus 2D chiplets.
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Kulicke & Soffa APTURA is a thermo-compression bonder for advanced packaging, not a wire bonder catalog and not OSAT assembly.
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Besi Datacon 8800 CHAMEO is a hybrid-bonding die-attach platform for copper-to-copper and related advanced-package construction.
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HANMI Dual TC Bonder is a thermocompression bonding platform for HBM die stacking.
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AT&S high-performance IC substrates are build-up package substrates that connect advanced processors to system boards, not generic PCBs and not OSAT assembly.
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Intel EMIB is a 2.5D packaging technology that embeds a silicon interconnect bridge in the package substrate to connect neighboring dies without a full-size interposer.
View solutionIntel Foundry 3D stacking and 2.5D chiplet packaging family, including hybrid-bonding options described as Foveros Direct 3D. EMIB is a separate 2.5D bridge platform.
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Amkor SWIFT is a high-density fan-out packaging platform for fine-pitch RDL and multi-die construction.
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TSMC umbrella family of 3D silicon stacking and advanced packaging. CoWoS, TSMC-SoIC and InFO are constituent platforms listed separately.
View solutionTSMC CoWoS is a 2.5D advanced packaging platform that integrates logic dies and high-bandwidth memory on an interposer for high-performance computing and AI systems.
View solutionTSMC InFO is a wafer-level integrated fan-out packaging platform using high-density redistribution layers for mobile, network and high-performance computing integration.
View solutionTSMC-SoIC is a wafer-level frontend 3D chip-stacking platform for homogeneous and heterogeneous chiplets, distinct from CoWoS 2.5D packaging and InFO fan-out.
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