
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
TSMC CoWoS is a publicly named 2.5D advanced packaging platform that places logic dies and high-bandwidth memory on an interposer for high-performance computing and AI products.
Official TSMC pages describe Chip-on-Wafer-on-Substrate as a wafer-level integration service in volume production since 2012. Named interposer options include silicon (CoWoS-S), redistribution-layer (CoWoS-R) and local-silicon-interconnect (CoWoS-L) constructions; those remain capabilities of this platform rather than separate listings. CoWoS is a constituent of the 3DFabric family and is distinct from TSMC-SoIC frontend stacking and InFO fan-out. Interposer sizes, design rules and current service options should be confirmed on TSMC’s CoWoS pages.
3D V-Cache stacks an L3 cache tile on a CPU core-complex die using copper-to-copper hybrid bonding and TSVs. Official AMD materials call it the first x86 true 3D die stack, with much higher interconnect density versus 2D chiplets.
View solutionKulicke & Soffa APTURA is a thermo-compression bonder for advanced packaging, not a wire bonder catalog and not OSAT assembly.
View solutionBesi Datacon 8800 CHAMEO is a hybrid-bonding die-attach platform for copper-to-copper and related advanced-package construction.
View solutionHANMI Dual TC Bonder is a thermocompression bonding platform for HBM die stacking.
View solutionAT&S high-performance IC substrates are build-up package substrates that connect advanced processors to system boards, not generic PCBs and not OSAT assembly.
View solutionIntel EMIB is a 2.5D packaging technology that embeds a silicon interconnect bridge in the package substrate to connect neighboring dies without a full-size interposer.
View solution