
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
High-Performance IC Substrate Platform is a publicly named AT&S materials offering.
AT&S high-performance IC substrates are build-up package substrates that connect advanced processors to system boards, not generic PCBs and not OSAT assembly.
Official AT&S IC-substrate pages describe high-density build-up substrates, flip-chip interconnect and fine-line copper for processors used in AI, data-center and automotive systems. This listing records IC substrates rather than AT&S printed-circuit-board businesses. Linewidth and glass-core development claims should be taken from AT&S’s current substrate pages.
3D V-Cache stacks an L3 cache tile on a CPU core-complex die using copper-to-copper hybrid bonding and TSVs. Official AMD materials call it the first x86 true 3D die stack, with much higher interconnect density versus 2D chiplets.
View solutionKulicke & Soffa APTURA is a thermo-compression bonder for advanced packaging, not a wire bonder catalog and not OSAT assembly.
View solutionBesi Datacon 8800 CHAMEO is a hybrid-bonding die-attach platform for copper-to-copper and related advanced-package construction.
View solutionHANMI Dual TC Bonder is a thermocompression bonding platform for HBM die stacking.
View solutionIntel EMIB is a 2.5D packaging technology that embeds a silicon interconnect bridge in the package substrate to connect neighboring dies without a full-size interposer.
View solutionIntel Foundry 3D stacking and 2.5D chiplet packaging family, including hybrid-bonding options described as Foveros Direct 3D. EMIB is a separate 2.5D bridge platform.
View solution