
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
Intel Foveros is a family of advanced packaging technologies used to place and interconnect multiple dies in one package.
Public Intel Foundry pages describe Foveros-S 2.5D assembly on a silicon interposer, Foveros-R 2.5D using redistribution-layer fan-out, and Foveros Direct 3D, which uses copper-to-copper hybrid bonding for vertical stacking. Those named Foveros variants remain capabilities of this family rather than separate listings. Intel also notes compatibility with chiplet interconnect approaches such as UCIe. EMIB, a silicon-bridge 2.5D interconnect described on the same Foundry packaging pages, is listed independently. Process options, design rules and current availability should be confirmed on Intel’s official packaging pages.
Distinct from Intel EMIB, which is a separate 2.5D embedded-bridge platform
3D V-Cache stacks an L3 cache tile on a CPU core-complex die using copper-to-copper hybrid bonding and TSVs. Official AMD materials call it the first x86 true 3D die stack, with much higher interconnect density versus 2D chiplets.
View solutionKulicke & Soffa APTURA is a thermo-compression bonder for advanced packaging, not a wire bonder catalog and not OSAT assembly.
View solutionBesi Datacon 8800 CHAMEO is a hybrid-bonding die-attach platform for copper-to-copper and related advanced-package construction.
View solutionHANMI Dual TC Bonder is a thermocompression bonding platform for HBM die stacking.
View solutionAT&S high-performance IC substrates are build-up package substrates that connect advanced processors to system boards, not generic PCBs and not OSAT assembly.
View solution