
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
TSMC-SoIC is TSMC’s publicly named wafer-level frontend 3D stacking platform for re-integrating chiplets into a compact stacked chip.
Official TSMC 3DFabric pages describe SoIC as a high-density bonding service that can later be assembled with conventional packages or with backend 3DFabric services such as CoWoS. Chip-on-wafer and wafer-on-wafer schemes are described as capabilities of this platform, not as independent listings. SoIC is grouped under the 3DFabric family and is distinct from CoWoS 2.5D interposer packaging and from InFO fan-out. Bonding pitches, node compatibility and service options should be confirmed on TSMC’s SoIC pages.
Wafer-level frontend 3D chip stacking for homogeneous and heterogeneous chiplets
3D V-Cache stacks an L3 cache tile on a CPU core-complex die using copper-to-copper hybrid bonding and TSVs. Official AMD materials call it the first x86 true 3D die stack, with much higher interconnect density versus 2D chiplets.
View solutionKulicke & Soffa APTURA is a thermo-compression bonder for advanced packaging, not a wire bonder catalog and not OSAT assembly.
View solutionBesi Datacon 8800 CHAMEO is a hybrid-bonding die-attach platform for copper-to-copper and related advanced-package construction.
View solutionHANMI Dual TC Bonder is a thermocompression bonding platform for HBM die stacking.
View solutionAT&S high-performance IC substrates are build-up package substrates that connect advanced processors to system boards, not generic PCBs and not OSAT assembly.
View solutionIntel EMIB is a 2.5D packaging technology that embeds a silicon interconnect bridge in the package substrate to connect neighboring dies without a full-size interposer.
View solution