Interface IP for links off the chip and between dies. PCIe is one category. A protocol name is the category to check; it is not proof that a controller and a PHY are the same listing.
Chevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.
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Chip Interfaces MIPI I3C Controller IP is licensable silicon-agnostic controller/target IP. The official page states compliance with MIPI I3C v1.1.1 and TCRI v1.0 for ASIC and FPGA.
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Comcores Ethernet Controller is licensable ASIC-proven network interface IP. The official page states 10M–10GbE speeds with integrated DMA, timestamping, flexible host interfaces, and RTL deliverables.
View solutionCommsonic Digital Communications IP is a licensable portfolio of DVB and related PHY modulator/demodulator/codec cores. The official home and products pages state gate- and power-efficient PHY IP for ASIC and FPGA.
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CoreTSE is triple-speed Ethernet MAC IP for supported Microchip FPGAs. The page documents operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s, which it also writes as 10/100/1000 Mbps. The PHY connects through G/MII or an SGMII ten-bit interface and stays a separate part. CoreTSE_AHB is a distinct AHB and DMA configuration. Both cores are included in the CoreTSE_AHB license, and this listing is only CoreTSE.
View solutionCoreTSE_AHB is triple-speed Ethernet MAC IP for supported Microchip FPGAs, with an AMBA AHB initiator and an integrated DMA engine. The page documents 10 Mb/s, 100 Mb/s, and 1 Gb/s. The PHY stays external, through G/MII or a ten-bit interface. This is not the CoreTSE configuration, which does not document that AHB and DMA path. Both cores are included in the CoreTSE_AHB license.
View solutionCorigine USB 3.2 Controller IP is licensable USB controller IP for ASIC and FPGA. The official USB IP page states USB-IF certified controllers for USB 3.2 Gen1/Gen2 and USB 2.0 with Host, Device, and DRD configurations.
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Credo SerDes is high-speed serializer/deserializer silicon and IP for data-center and AI interconnect, not a compute accelerator architecture.
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Creonic DVB-S2X decoder is licensable silicon-proven LDPC/BCH decoder IP. The official page states DVB-S2/S2X compliance with VHDL source or netlist deliverables for ASIC and FPGA.
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Curious Camera PHY Interface IP is licensable camera physical-layer and link soft-macro IP. The official English interface page lists MIPI D-PHY (and related camera PHYs) with foundry/node supply tables and separate CSI-2 link soft macros.
View solutionDCD DCAN FD is licensable CAN FD controller soft IP. The official product page states ISO 11898-1:2015 / CAN FD compliance with VHDL/Verilog/netlist deliverables for FPGA and ASIC.
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Design Gateway USB3.0-IP is licensable USB 3.0 host or device controller soft IP for AMD FPGAs. The official page states USB 3.0 Revision 1.0 compliance for link and protocol layers with PIPE PHY interface.
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