Public source

Design Gateway USB 3.0 Host/Device IP Core

The USB3.0-IP core page reviewed on 12 November 2026 states compliance with the USB 3.0 specification Revision 1.0 and operation on AMD 7-Series, Spartan-6, and Virtex-6 devices.

Solution category: USB IP
Offering type: Product

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Overview

Design Gateway USB3.0-IP is licensable USB 3.0 host or device controller soft IP for AMD FPGAs.

It provides link and protocol layers and interfaces to a TI PHY chip over a 16-bit PIPE interface (page notes TI TUSB1310A is not recommended for new designs). Features include Host or Device controller modes, adjustable clocks (250 MHz PIPE; >125 MHz internal), up to 15 endpoints (1 control + 7 IN + 7 OUT), Control/Bulk/Isochronous/Interrupt transfers, and a simple transaction or DMA interface. Free time-limited evaluation bit files and datasheets for Host-IP and Device-IP are listed for boards such as ZC706, VC707, KC705, SP605, and ML605. Official page confirms purchasable IP with evaluation bit files and datasheets.

Technical capabilities

Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
USB 3.0 host/device controller
Numbered specification: USB 3.0 Revision 1.0
USB 3.0 Revision 1.0 is named for this product on the reviewed page.
Recorded aliases
Design Gateway USB3.0-IP; DG USB3 Host-IP; DG USB3 Device-IP

Lifecycle and categories

Lifecycle stages: Interface and connectivity IP
Solution categories: USB IP
Supported versions: USB 3.0 Revision 1.0
Compatibility: AMD 7-Series/Spartan-6/Virtex-6; 16-bit PIPE to external PHY. Source