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Faststream AXI USB 2.0 Device IP (Semiconductor IP Catalogue)

The Semiconductor IP page reviewed on 12 November 2026 states Faststream licenses semiconductor IP cores for digital, analog and mixed-signal integration with verification collateral and integration support.

Overview

The official Semiconductor IP page lists USB, PTP, AXI-oriented, DSP, SERDES and related cores with licence/delivery process.

The core catalogue table includes AXI USB 2.0 Device IP (USB 2.0 device controller with AXI interface), Precision Time Protocol IP (IEEE 1588 including automotive Ethernet variant), Analog Data Acquisition Controller IP, Multi-Protocol Synchronous Serial Engine IP, 18-bit Pipeline DSP Slice IP, ADC IP, SERDES, PVT sensors, ultra-low-jitter clocking, memory interfaces and I/O, a posit-based processor, Ethernet CAN-to-ALDL bridge, Ethernet PID-control filters, and Verification IP. Maturity is stated to vary (silicon-proven, FPGA-validated, or RTL) and confirmed at enquiry. Licence flow covers requirements/fit, configuration, delivery with documentation and verification collateral, integration support, and lifecycle updates. The catalogue is also published on Design & Reuse.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    USB 2.0 device controller

  • Numbered specification: USB 2.0 Device (AXI)

    USB 2.0 Device (AXI) is named for this product on the reviewed page.

  • Numbered specification: catalogue also lists IEEE 1588 PTP and other cores

    catalogue also lists IEEE 1588 PTP and other cores is named for this product on the reviewed page.

Lifecycle and categories

Solution categories
USB IP
Supported versions
USB 2.0 Device (AXI); catalogue also lists IEEE 1588 PTP and other cores
Compatibility
SoC integration with verification collateral; node bands 180–90 nm through 28 nm and below described. Source

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