Chip Interfaces MIPI I3C Controller IP

Chip Interfaces MIPI I3C Controller IP is licensable silicon-agnostic controller/target IP.

It states the IP can act as Bus Controller or Secondary Controller, and with the Target Engine as a Target or Composite Device with multiple Virtual Targets. Documented support includes SDR and HDR modes (HDR-DDR, HDR-TSP/TSL, HDR-BT), multi-lane operation, speeds up to 100 Mbps, Hot Join, all I3C CCC codes, Async Modes 0–3, Target Reset, Device-to-Device tunneling, Early Termination, and TCRI v1.0 application data interface. Backward compatibility with MIPI I3C 1.1/1.0 and I2C is stated. Deliverables include source or encrypted RTL, documentation, simulation environment, synthesis scripts, and SDC timing constraints. The page states UVM-based verification and lint/CDC checking.