
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The DVB-S2X BCH and LDPC Decoder IP Core page reviewed on 12 November 2026 describes a silicon-proven, scalable decoder allowing symbol rates up to 100 MSymbols/s on state-of-the-art FPGAs.
It states compliance with DVB-S2 and DVB-S2X, BBFRAME decoding, ACM/CCM/VCM, VLSNR modes below −9 dB, short/medium/normal frames (16,200 / 32,400 / 64,800 bits), and modulations from BPSK through 256-APSK. Benefits listed include soft-decision demapper, block deinterleaver, LDPC and BCH decoders, descrambler and CRC checks, layered LDPC architecture, early stopping, on-the-fly configuration, and statistics collection. Deliverables include VHDL source or synthesized netlist, HDL simulation models, VHDL or SystemC testbench, and bit-accurate Matlab/C/C++ models for ASICs and FPGAs (AMD/Xilinx, Intel/Altera, Microchip). Address Bahnhofstraße 26-28, 67655 Kaiserslautern, Germany is listed.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
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DVB-S2X LDPC/BCH decoder
Numbered specification: DVB-S2 and DVB-S2X
DVB-S2 and DVB-S2X is named for this product on the reviewed page.
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