Memory and subsystem IP

SRAM, embedded memory, memory controllers and PHYs.

Showing 25–36 of 43 solutions.

Provider

SK hynix HBM4
Memory and subsystem IP
SK hynix HBM4 doubles I/O to 2,048 terminals, claims >10 Gbps and more than 40% better power efficiency versus the prior generation, and uses Advanced MR-MUF to stack DRAM with warpage control and heat dissipation.
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Samsung HBM4
Memory and subsystem IP
Samsung HBM4 is the company’s current high-bandwidth DRAM stack for AI accelerators, with an advanced base die and stacked DRAM cubes. Samsung’s official HBM family page covers HBM3E through HBM4/HBM4E as the AI-memory roadmap.
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SkyeChip HBM3/3E PHY & Controller
DDR & HBM IP
SkyeChip HBM3/3E PHY & Controller is a licensable one-stop memory-interface IP solution. The official IP Solutions page states JEDEC HBM3 (JESD238A) conformance with rates up to 6400 MT/s (HBM3) and 9600 MT/s (HBM3E) and a DFI 5.1 PHY-to-controller interface.
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So-Logic SATA-III Host Controller IP Core
Memory Controllers
So-Logic so_ip_sata3_hctrl is licensable SATA host-controller soft IP. The official page states SATA Specification 3.2 compliance with 1.5/3.0/6.0 Gbit/s rates for Xilinx FPGAs.
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Synopsys DDR5/4 Controller IP
Memory Controllers
Synopsys DDR5/4 Controller IP is DesignWare memory-controller IP. The reviewed page says it supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs and connects to a PHY through DFI 5.0. It is not the DDR PHY.
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Synopsys DDR5/4 PHY IP
DDR & HBM IP
Licensable DDR5 and DDR4 PHY IP. The page documents up to 8400 Mb/s, DFI 5.0, and a hard PHY. A memory controller is not included.
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Synopsys HBM Interface IP
DDR & HBM IP
Synopsys HBM interface IP is a high-bandwidth memory interface family including controller, PHY and verification IP for AI and high-performance computing SoCs. Distinct from UCIe die-to-die IP.
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Synopsys LPDDR5X/5/4X Controller IP
Memory Controllers
Licensable design IP. Digital memory controller for LPDDR5X, LPDDR5, and LPDDR4X. The PHY is separate.
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True Circuits PLL / DLL / DDR PHY Hard MacrosTrue Circuits, Inc.
DDR & HBM IP
True Circuits PLL, DLL, and DDR PHY hard macros are licensable mixed-signal timing and memory-interface IP. The official product matrix links datasheets for standard hard macros across TSMC nodes with DDR rates up to 6400 MT/s on advanced nodes.
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Uniquify High-Speed Adaptive DDR Interface IP
DDR & HBM IP
Uniquify Adaptive DDR Interface is licensable DDR/LPDDR/HBM memory-interface IP. The official IP page states patented adaptive technologies for PVT variation, covering DDR3/4/5, LPDDR3/4/5, and HBM across foundries from 65 nm to 7 nm.
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Weebit ReRAM
Embedded Memory IP
Weebit ReRAM is embedded resistive-RAM IP, not a discrete DRAM or NAND catalog.
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Xenergic High-Speed Low-Power SRAM IP
Embedded Memory IP
Xenergic HSLP SRAM is licensable on-chip SRAM IP. The official High-Speed Low-Power page states customer cases with up to 40% lower dynamic power and up to 55% lower leakage while maintaining speed and competitive area.
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