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Xenergic High-Speed Low-Power SRAM IP

The Xenergic High-Speed Low-Power SRAM page reviewed on 12 November 2026 positions HSLP SRAM IP as balancing power and performance for sensors, wearables, IoT, and edge computing.

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Overview

Xenergic HSLP SRAM is licensable on-chip SRAM IP. The official High-Speed Low-Power page states customer cases with up to 40% lower dynamic power and up to 55% lower leakage while maintaining speed and competitive area.

Broader memory-offering pages describe single-rail memories using foundry-provided bitcells, standard memory interfaces with DFT views, and support for redundancy, ECC, sleep modes, and periphery body biasing via the MemoryTailor compiler. Related product families named include Ultra High-Speed SRAM and High-Speed Turbo Memory. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    Low-power SRAM

  • Recorded aliases

    Xenergic HSLP; Xenergic SRAM; MemoryTailor

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Embedded Memory IP
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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