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Public source

So-Logic SATA-III Host Controller IP Core

The SATA-III Host Controller Core page reviewed on 12 November 2026 describes so_ip_sata3_hctrl as a soft core implementing physical, link, and transport layers per SATA Specification 3.2, supporting 1.5, 3.0, and 6.0 Gbit/s.

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Overview

The official page states SATA Specification 3.2 compliance with 1.5/3.0/6.0 Gbit/s rates for Xilinx FPGAs.

It states use of Xilinx RocketIO GTP/GTX for physical signaling, a PATA-style host-processor interface, and a simple TX/RX DMA transaction interface. Features include 32-bit datapath, 8 KB TX/RX BlockRAM FIFOs, speed auto-negotiation, 48-bit addressing, 8b/10b, CRC, NCQ, Port Multiplier/Selector, FPDMA, CONT primitive support, and shadow/status registers. Supported families listed: Zynq-7000, Artix-7, Kintex-7, Virtex-7/6/5 with ISE/Vivado. Licensing options include post-synthesis netlist or VHDL source with testbenches; evaluation bit files are offered. Official datasheet-style page with netlist/VHDL license options.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    SATA host controller

  • Numbered specification: SATA Specification 3.2 (1.5/3.0/6.0 Gbit/s)

    SATA Specification 3.2 (1.5/3.0/6.0 Gbit/s) is named for this product on the reviewed page.

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Memory Controllers
Supported versions
SATA Specification 3.2 (1.5/3.0/6.0 Gbit/s)
Compatibility
Xilinx GTP/GTX RocketIO; Zynq-7000 and 7/6/5-series families listed. Source

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