
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
Samsung HBM4 is a publicly named high-bandwidth memory device family for AI accelerators.
Samsung HBM4 is the company’s current high-bandwidth DRAM stack for AI accelerators, with an advanced base die and stacked DRAM cubes. Samsung’s official HBM family page covers HBM3E through HBM4/HBM4E as the AI-memory roadmap.
This listing records Samsung’s HBM4 stack technology rather than every HBM generation. HBM3 and HBM3E remain prior generations of the same family rather than separate listings. Micron High-Bandwidth Memory and Synopsys HBM Interface IP, already in the catalog, are a different vendor’s device and a PHY/controller IP block. Capacity options and interface details should be taken from Samsung’s current HBM documentation.
Positioned for AI accelerator and data-center platforms
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
View solutionLicensable standalone last-level cache IP for a non-coherent AXI4 interface. It is not a cache-coherent NoC, not a DDR controller, and not an OTP.
View solutionAttopsemi I-fuse is licensable OTP memory IP based on a non-explosive fuse programming mechanism. The official technology page states foundry-independent OTP without extra masks and physics-based electro-migration programming.
View solutionLicensable design IP. DDR and LPDDR controller for LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
View solutionLicensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.
View solution