
SC26
- November 15 – 20, 2026
- Chicago, Illinois, USA
- Organized by SC Conference Series
Public source
SK hynix HBM4 is a publicly named high-bandwidth DRAM stack.
A 19 March 2025 newsroom post describes 12-layer HBM4 samples. This listing records SK hynix’s HBM4 and MR-MUF stack, not HBM3E as a second row. Samsung HBM4 and Micron HBM are other vendors’ implementations of the same device class. Layer counts and bandwidth figures should be confirmed on SK hynix’s current newsroom and product pages.
HBM4 stack with 2,048 I/O terminals
Advanced MR-MUF molding between DRAM dies
Official materials describe 12-layer samples and mass-production readiness
Distinct from Samsung HBM4 stacking and Micron HBM devices
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
View solutionLicensable standalone last-level cache IP for a non-coherent AXI4 interface. It is not a cache-coherent NoC, not a DDR controller, and not an OTP.
View solutionAttopsemi I-fuse is licensable OTP memory IP based on a non-explosive fuse programming mechanism. The official technology page states foundry-independent OTP without extra masks and physics-based electro-migration programming.
View solutionLicensable design IP. DDR and LPDDR controller for LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
View solutionLicensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.
View solution