Memory & Subsystem IP
Controllers that schedule reads and writes to DRAM. Pair this with a DDR or HBM interface only when the design needs both.
So-Logic so_ip_sata3_hctrl is licensable SATA host-controller soft IP. The official page states SATA Specification 3.2 compliance with 1.5/3.0/6.0 Gbit/s rates for Xilinx FPGAs.
View solutionSynopsys DDR5/4 Controller IP is DesignWare memory-controller IP. The reviewed page says it supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs and connects to a PHY through DFI 5.0. It is not the DDR PHY.
View solutionLicensable design IP. Digital memory controller for LPDDR5X, LPDDR5, and LPDDR4X. The PHY is separate.
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YEESTOR LDPC IP is licensable NAND flash ECC encode/decode IP. The official Chinese product page states soft/hard decoding, configurable throughput, and a complete development package for FPGA and SoC use.
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ZeroPoint ZeroStream is licensable hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces. The official products page states line-rate pipelined compression with deterministic latency for HBM, LPDDR, DDR, and chip-to-chip/CXL links.
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