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Public source

YEESTOR LDPC Encoder/Decoder IP

The LDPC IP page reviewed on 12 November 2026 (Chinese) describes YEESTOR LDPC as an error-correction encode/decode engine for storage data, targeting mobile, consumer, and enterprise SSD controller markets and supporting various 2D/3D SLC/MLC/TLC/QLC NAND Flash.

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Overview

The official Chinese product page states soft/hard decoding, configurable throughput, and a complete development package for FPGA and SoC use.

Stated parameters include support for 1KB+/2KB+/4KB+ code lengths, configurable throughput, soft and hard decoding, hard/soft decode UBER below 10^-17 at 4K code length, built-in low-power handling, up to 6-bit soft decoding, variable code rate, parity check, dynamic code switching and error monitoring, out-of-order decoding, and configurable termination. The page states validation on YEESTOR platforms with NAND Flash and AWGN channel models, and prior mass-production verification in USB, eMMC, and consumer/enterprise SSD domains. Deliverables listed include RTL code, RTL test environment, C LDPC codec library, templates, calibration tools, ASIC/FPGA synthesis scripts, and a programming guide.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Finder function

    NAND LDPC ECC

  • Numbered specification: LDPC ECC for NAND (code lengths 1KB+/2KB+/4KB+ stated)

    LDPC ECC for NAND (code lengths 1KB+/2KB+/4KB+ stated) is named for this product on the reviewed page.

  • Recorded aliases

    YEESTOR LDPC IP; 得一微 LDPC

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Memory Controllers
Supported versions
LDPC ECC for NAND (code lengths 1KB+/2KB+/4KB+ stated)
Compatibility
FPGA and SoC development package stated; NAND Flash types SLC/MLC/TLC/QLC. Source

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