Cadence Xcelium Logic Simulator
SimulationCadence Xcelium is a logic simulator for SystemVerilog, VHDL, SystemC, e, UVM, mixed-signal, and low-power verification. It is an EDA tool, not design IP.
View solutionDesign & Verification
Tools and verification IP used before implementation. A tool listing describes that product; it does not certify another vendor’s IP.
Showing 13–24 of 28 solutions.
Cadence Xcelium Logic Simulator
SimulationDapTechnology IEEE-1394 / AS5643 IP Cores (FireGate / FireLink / FireCore)
IP Portfolios
DapTechnology offers synthesizable IEEE-1394b and AS5643 IP cores (PHY, Link, and combined). Official home and IP Core pages describe FireGate PHY, FireLink LLC, and FireCore packages with NetList/Source/Deployment licenses.
View solutionGoogle Cloud infrastructure for semiconductor EDA
EDA Infrastructure
Cloud infrastructure for semiconductor design and verification workloads.
View solutionLibero SoC Design Suite
FPGA Development Tools
Libero SoC Design Suite is FPGA development software for designing with Microchip FPGA families. The reviewed page describes RTL entry through programming, block-based design, RTL debug, an integrated logic analyzer, simulation, an IP library, and production programming. It is not semiconductor IP and not an ASIC physical-design tool.
View solutionMenta eFPGA Soft IP
eFPGA IPMenta eFPGA Soft IP is licensable embedded FPGA IP delivered as Soft RTL or Hard GDSII. The official Soft IP page states 100% standard-cell-based portability with silicon-proven results across many foundry nodes.
View solutionPolarFire SoC FPGA
SoC FPGAPolarFire SoC FPGA is a finished programmable device with a hardened, coherent RISC-V cluster and FPGA fabric. Microchip documents that cluster for Linux and real-time software. The transceiver devices in the reviewed table are MPFS025T, MPFS095T, MPFS160T, MPFS250T, and MPFS460T. PolarFire Core SoC FPGAs are cost-optimized variants without high-speed SerDes and without PCIe Gen2 endpoints or root ports. This device is not the Mi-V RV32 soft CPU and not licensable IP.
View solutionQuickLogic eFPGA Hard IP
eFPGA IP
QuickLogic describes customizable eFPGA hard IP, generated from standard-cell ASIC libraries for a chosen process and foundry, with LUT6, BRAM, and DSP resources set for the engagement.
View solutionRenesas IP products and licenses
IP Portfolios
A documented licensable IP portfolio for chip and subsystem development.
View solutionSiemens Questa One
SimulationSiemens Questa One is a verification suite whose page names simulation, debug, static, and formal engines. Individual engines are not separated here.
View solutionSiemens Veloce Strato CS
EmulationSiemens Veloce Strato CS is an emulation platform. Its stated capacity is a scaling range, not the capacity of every configuration.
View solutionSmartDV MIPI M-PHY VIP
Verification IP
SmartDV MIPI M-PHY VIP is verification IP for the MIPI M-PHY physical layer. The product page labels it Verification IP, not design/silicon PHY IP. It states compliance with MIPI M-PHY v6.0 and backward compatibility with v5.0, v4.1, and v3.0.
View solutionSynopsys VC Formal
Formal VerificationSynopsys VC Formal is a formal verification tool for SoC RTL, including property, connectivity, register, and equivalence apps. It is an EDA tool, not design IP.
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