Synopsys VCS
SimulationSynopsys VCS is a functional-verification simulator with SystemVerilog and UVM support, coverage, and debug integration. It is an EDA tool, not design IP.
View solutionDesign & Verification
Tools and verification IP used before implementation. A tool listing describes that product; it does not certify another vendor’s IP.
Showing 25–28 of 28 solutions.
Synopsys VCS
SimulationSynopsys ZeBu-200
EmulationSynopsys ZeBu-200 is a hardware emulation platform for long-running RTL, software, and power workloads. It is an emulation system, not a multi-project wafer shuttle.
View solutionTruechip UFS 5.0 Verification IP
Verification IP
Truechip UFS 5.0 Verification IP is VIP for JEDEC UFS host/device verification. The official page states compliance with UFS 5.0/4.0/3.1/3.0 and native SystemVerilog UVM/OVM/VMM deliverables.
View solutionproteanTecs on-chip monitoring IP and analytics
Silicon Monitoring
Embedded monitoring IP with software for chip health and performance analysis.
View solution
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