
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The product page describes the hardened cluster for Linux and real-time applications.
PolarFire SoC FPGA is a finished programmable device with a hardened, coherent RISC-V cluster and FPGA fabric. Microchip documents that cluster for Linux and real-time software. The transceiver devices in the reviewed table are MPFS025T, MPFS095T, MPFS160T, MPFS250T, and MPFS460T. PolarFire Core SoC FPGAs are cost-optimized variants without high-speed SerDes and without PCIe Gen2 endpoints or root ports. This device is not the Mi-V RV32 soft CPU and not licensable IP.
The microprocessor subsystem table states one E51 RV64IMAC boot and monitor core and four U54 RV64GC application cores, each at 625 MHz, plus a 2 MB L2 that can be cache, loosely integrated memory, or scratchpad. Logic elements in that table are 23K, 93K, 161K, 254K, and 461K. The Core SoC paragraph says up to 460K logic elements. Two Gigabit Ethernet MACs are hardened subsystem peripherals, not the CoreTSE IP core. SerDes lanes on the transceiver devices are stated from 250 Mbps to 12.50 Gb/s per lane. A crypto coprocessor is stated for devices whose ordering code ends in S. Speed grade, temperature, and package need confirmation. Pricing is not part of this listing.
Finder function
SoC FPGA
Configuration checks
Confirm the density, package, and whether the device is a transceiver PolarFire SoC or a PolarFire Core SoC. Do not apply this device's Linux support to Mi-V RV32.
Recorded aliases
PolarFire SoC; PolarFire Core SoC; MPFS

