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QuickLogic eFPGA Hard IP

QuickLogic describes customizable eFPGA hard IP, generated from standard-cell ASIC libraries for a chosen process and foundry, with LUT6, BRAM, and DSP resources set for the engagement.

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Overview

This is embedded FPGA IP for an SoC. It is not one of QuickLogic’s finished FPGA devices. The retired australis-efpga slug is not reused. Confirm the foundry, process, array size, and bitstream-security option. No single array size is assumed.

Technical capabilities

  • Availability

    Listed by the provider. Confirm the configuration before use.

  • Implementation target

    ASIC SoC

  • Finder function

    eFPGA IP

Lifecycle and categories

Solution categories
eFPGA IP
Compatibility
Pricing, licensing, and configuration availability require provider confirmation. Source

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