
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Speedcore Embedded FPGA IP page reviewed on 12 November 2026 describes Speedcore eFPGA IP integrated into ASICs/SoCs for high-performance compute-intensive and real-time applications including AI/ML, 5G wireless, networking, storage and automotive.
The official product page states silicon-proven eFPGA technology with selectable logic, DSP/MLP and memory resources and Achronix Tool Suite programming.
It states customers license eFPGA IP similarly to other semiconductor IP and can select exact logic, DSP (or MLP) and memory resources, lowering cost/power/board space versus a discrete FPGA. Programming uses the Achronix Tool Suite with RTL synthesis, place and route, timing analysis and bitstream flow identical to a standalone FPGA, with a customer-specific eFPGA instance targeted in the tools. Product brief PB028 and timing-closure / SmartNIC / automotive white papers are linked. The page states Achronix is a high-end FPGA supplier providing both discrete FPGAs and eFPGA IP proven in production applications.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Finder function
eFPGA fabric
Numbered specification: Speedcore eFPGA (resource mix configured per customer instance)
Speedcore eFPGA (resource mix configured per customer instance) is named for this product on the reviewed page.
Recorded aliases
Speedcore; Achronix eFPGA; Speedcore eFPGA
ADICSYS eFPGA Soft IP is licensable standard-cell-based embedded FPGA IP. The official home page states the company designs and licenses soft eFPGA IP for ASICs and SoCs with technology-independent RTL-flow integration.
View solutionMenta eFPGA Soft IP is licensable embedded FPGA IP delivered as Soft RTL or Hard GDSII. The official Soft IP page states 100% standard-cell-based portability with silicon-proven results across many foundry nodes.
View solutionQuickLogic describes customizable eFPGA hard IP, generated from standard-cell ASIC libraries for a chosen process and foundry, with LUT6, BRAM, and DSP resources set for the engagement.
View solution
