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Interface and connectivity IP

PCIe, CXL, UCIe, Ethernet, USB, MIPI, DDR and HBM interfaces.

Showing 49–60 of 90 solutions.

Provider
  • M31 MIPI C-PHY/D-PHY ComboM31 Technology logo

    MIPI IP

    M31 MIPI C-PHY/D-PHY Combo is licensable PHY IP. The official page describes a configurable C-PHY or D-PHY physical layer with a PPI interface for CSI-2 and DSI controllers. MIPI CSI-2/DSI-2 controllers are separate M31 products.

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  • MAXVY MIPI CSI-2 v3 Transmitter IPMAXVY Technologies Pvt Ltd logo

    MIPI IP

    MAXVY MIPI CSI-2 Transmitter IP-V3 is licensable camera-serial-interface transmitter design IP. The product page states compliance with MIPI CSI-2 version 3.0 and lists Verilog source deliverables.

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  • Mixel MIPI D-PHY (MXL-DPHY)Mixel logo

    MIPI IP

    Mixel MIPI D-PHY (MXL-DPHY) is licensable PHY IP. The official page describes a physical layer compliant with MIPI D-PHY, delivered as soft digital CIL plus hard mixed-signal views. CSI-2/DSI controllers are separate from this PHY listing.

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  • Qualitas PCIe Gen4 to Gen6 PHY IPQualitas Semiconductor logo

    PCIe IP

    Qualitas PCIe PHY IP is licensable hard PHY IP covering PCI Express Gen4 through Gen6. The official English site states PCIe PHY delivering up to 64 GT/s per lane alongside UCIe, SerDes, MIPI, USB, and Ethernet PHY lines.

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  • RAMSCHIP ADC-Based SerDes IPRAMSCHIP logo

    SerDes IP

    RAMSCHIP ADC-based SerDes is licensable/custom high-speed SerDes IP. The official Technology section states high-speed SerDes including ADC-based SerDes and ML-based digital filters for automotive and related applications.

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  • Rafael Micro RF IP LicensingRafael Micro logo

    Wireless Protocol IP

    Rafael Micro RF IP is licensable RF/mixed-signal IP offered alongside RF-centric ASIC services. The official site states RF IP authorization and ASIC design services to help customers integrate RF functions into SoCs, spanning DC–28 GHz RF CMOS expertise.

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  • Rambus CXL 3.1 ControllerRambus logo

    CXL IP

    Licensable CXL controller IP. The page documents CXL 3.1, backward compatibility with CXL 2.0 and CXL 1.1, CXL.io, CXL.cache, and CXL.mem, and 64 GT/s. It is not a finished memory expander and does not include a PHY.

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  • Rambus PCIe 6.3 ControllerRambus logo

    PCIe IP

    Licensable PCIe controller IP. The page documents PCIe 6.3 with revisions 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.

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  • Silicon Interfaces PCIe 3.0 Controller IPSilicon Interfaces logo

    PCIe IP

    Silicon Interfaces PCIe 3.0 Controller IP is a licensable synthesizable RTL PCI Express controller core. The official AssetsPCIe page states a fully synthesizable Verilog HDL core with UVM testbench and optional VIP add-ons.

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